RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Register 0x81040: A1SP Receive Status FIFO (A1SP_RSTAT_FIFO)
Bit
Type
Function
Default
15:8
7:6
5
RO
RO
RO
RO
RO
RO
RO
RO
QUEUE_NUMBER[7:0]
Unused
X
X
X
X
X
X
X
X
R_LINE_RESYNC
T_LINE_RESYNC
BITMASK_CHANGE
EXIT_UNDERRUN
ENTER_UNDERRUN
RECEIVE_QUEUE_ERR
4
3
2
1
0
This register is the read port of a 64 word FIFO that is used to capture receive
status events on a first come first serve basis. If the FIFO overflows the
RSTAT_FIFO_FULL bit will be set in the A1SP_INTR_REG. The presence of
data in this FIFO will set the RSTAT_FIFO_EMPB bit in the A1SP_INTR_REG.
The RSTAT_EN_REG controls whether certain errors or status conditions cause
an entry to be written into the RSTAT_FIFO. There is a separate RSTAT_ FIFO
for each A1SP block.
RECEIVE_QUEUE_ERR
An error or status condition occurred on the receive queue identified in
QUEUE_NUMBER. Read sticky bit register for this queue to determine actual
event. The RCV_Q_ERR_EN register controls which Receive queue sticky
bits will cause an entry into this FIFO.
ENTER_UNDERRUN
The queue identified by QUEUE_NUMBER just entered the underrun state.
If the queue is in DBCES mode, this may also indicate that all channels have
gone idle.
EXIT_UNDERRUN
The queue identified by QUEUE_NUMBER just exited the underrun state.
BITMASK_CHANGE
This condition is only valid if DBCES mode has been enabled for this queue.
If the bit is set it indicates that the bitmask for active channels has changed.
Read R_CHAN_ACT in the R_QUEUE_TBL to determine current bit mask.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
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PMC [ PMC-SIERRA, INC ]
