RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Register 0x81150: Receive Queue Error Enable (RCV_Q_ERR_EN)
Bit
15
Type
Function
Default
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
CELL_RECEIVED
DBCES_BM_ERR
PTR_RULE_ERROR
ALLOC_TBL_BLANK
POINTER_SEARCH
FORCED_UNDERRUN
SN_CELL_DROP
POINTER_RECEIVED
PTR_PARITY_ERR
SRTS_RESUME
SRTS_UNDERRUN
RESUME
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
14
13
12
11
10
9
8
7
6
5
4
3
2
PTR_MISMATCH
OVERRUN
1
0
UNDERRUN
The above enable bits control what is done when R_ERROR_STKY bits are set
in the R_QUEUE_TBL. It controls which types of error/status conditions cause
the RECEIVE_QUEUE_ERR indication in the RCV_STAT_FIFO to be set. All
queues are configured the same way. Only the first enabled condition which
occurs for a given queue will cause an entry to be made in the RCV_STAT_FIFO
until the sticky bit register is cleared. So usually you should only enable bits that
will not occur normally.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
273
PMC [ PMC-SIERRA, INC ]
