RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Register 0x81030: A1SP Transmit Idle State FIFO (A1SP_TIDLE_FIFO)
Bit
Type
Function
Default
15:0
RO
CHAN_STATUS
See description
below
X
This register is the read port of a 64 word FIFO that is used to indicate changes
in the activity status (active or idle) on a given channel on a first come first serve
basis. If the FIFO overflows the TX_IDLE_FIFO_FULL bit will be set in the
A1SP_INTR_REG. When this FIFO goes from an empty to a non-empty
condition the TX_IDLE_FIFO_EMPB bit in the A1SP_INTR_REG will be set. The
presence of data in this FIFO will set the TX_IDLE_FIFO_EMPB bit in the
A1SP_STAT_REG. Read A1SP_STAT_REG to determine when FIFO goes
empty again. If idle detection is not enabled on a given channel then the channel
will not write to this FIFO.
CHAN_STATUS
This register structure is dependent on which of the two idle detection modes
is used: automatic or processor. The idle detection mode is controlled by the
value of IDLE_CFG_Ln_Cx for the respective line and channel number in the
Idle Configuration Detection Table. The structure for automatic idle detection
is shown first followed by the structure for processor idle detection.
Automatic Idle Detection with either CAS or Pattern Matching
In this mode when either CAS or Pattern Matching indicates a change in the
active status of a channel, an entry will be written into the FIFO depending on the
state of IDLE_CFG_Ln_Cx for that channel.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
265
PMC [ PMC-SIERRA, INC ]
