PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
8.10 Jitter Characteristics of Clock Synthesis Logic
This section shows the results of jitter analysis of the clock synthesis circuitry built into the
AAL1gator II. Jitter was measured using a FIREBERD 6000A with the E1 or T1 jitter analyzer
option and the jitter spectrum analysis option added. The clock synthesis logic is intended to be
used with an external jitter attenuator. Results are shown with and without the jitter attenuator in a
Level One LXT305A LIU enabled.
8.10.1 Nominal T1 Clock
20
The nominal T1 clock jitter was measured using a 2 -1 Pseudorandom Bit Sequence (PRBS)
pattern in unstructured mode. The total maximum jitter without the jitter attenuator was 0.40 Unit
Interval (UI). With a jitter attenuator the maximum jitter was 0.08 UI. See Figure 96 and
Figure 97 for the jitter spectrum versus the G.824 mask.
10
1
G.824 Mask
0.1
Jitter
0.01
0.001
1
10
100
1000
10000
100000
Frequency(Hz)
Figure 96. Nominal T1 Clock with no Jitter Attenuator
ꢀꢇꢄ
PMC [ PMC-SIERRA, INC ]
