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PM73121-RI 参数 Datasheet PDF下载

PM73121-RI图片预览
型号: PM73121-RI
PDF下载: 下载PDF文件 查看货源
内容描述: AAL1分段重组处理器 [AAL1 Segmentation And Reassembly Processor]
分类和应用: ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 223 页 / 2148 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM73121AAL1gator II  
Data Sheet  
PMC-Sierra, Inc.  
PMC-980620  
,VVXHꢀꢁ  
AAL1 SAR Processor  
Table 8. T1/E1 Interface Signals (Continued)  
Reset  
Signals  
Pin #  
Type  
Description  
Value*  
RL_MSYNC(7)  
RL_MSYNC(6)  
RL_MSYNC(5)  
RL_MSYNC(4)  
RL_MSYNC(3)  
RL_MSYNC(2)  
RL_MSYNC(1)  
RL_MSYNC(0)  
160  
147  
135  
123  
107  
95  
In  
NA  
Receive Line Multiframe Synchronization Bits 7 to 0 carry the  
multiframe timing information from the corresponding framer  
device. These signals do not need to indicate the start of each  
and every multiframe - they can occur infrequently. Each time  
one of these signals has an edge to indicate the start of a  
multiframe, the AAL1gator II re-aligns the multiframe  
76  
64  
according to where the edge occurred. Tie to ground if not used.  
RL_FSYNC(7)  
RL_FSYNC(6)  
RL_FSYNC(5)  
RL_FSYNC(4)  
RL_FSYNC(3)  
RL_FSYNC(2)  
RL_FSYNC(1)  
RL_FSYNC(0)  
159  
146  
134  
118  
106  
94  
In  
NA  
Receive Line Frame Synchronization Bits 7 to 0 carry the  
receive frame information from the corresponding framer  
devices in the SDF-MF and SDF-FR modes. The bits originate  
from the corresponding framer bits.  
75  
63  
RL_CLK(7)  
RL_CLK(6)  
RL_CLK(5)  
RL_CLK(4)  
RL_CLK(3)  
RL_CLK(2)  
RL_CLK(1)  
RL_CLK(0)  
158  
145  
133  
117  
105  
86  
In  
NA  
Receive Clock Bits 7 to 0 form an 8-bit bus. The bits originate  
from the corresponding framer bits 0 to 7. In the UDF-HS  
mode, only line 0 is active.  
74  
58  
SRTS_DOUT(3:0)  
35-38  
Out  
Out  
0
0
SRTS Data Out Bits 3 to 0 form the SRTS correction code when  
SRTS_STRB is asserted; otherwise SRTS_DOUT bits form the  
channel status and frame difference when ADAP_STRB is  
asserted.  
SRTS_LINE(3)  
SRTS_LINE(2:0)  
47  
39-41  
SRTS Line Bits 3 to 0 indicate the T1/E1 line that SRTS_DOUT  
corresponds to when SRTS_STRB is asserted; otherwise  
SRTS_LINE bits form the adaptive state machine index when  
ADAP_STRB is asserted.  
SRTS_STRB  
ADAP_STRB  
N_CLK  
42  
43  
45  
Out  
Out  
In  
0
0
SRTS Strobe indicates that an SRTS value is present on SRTS_  
DOUT(3:0) and SRTS_LINE(2:0). This transfer is made  
synchronous to SYS_CLK.  
Adaptive Strobe indicates that the channel status and frame  
difference are being played out on the SRTS_DOUT. The  
nibbles are identified by the values on SRTS_LINE.  
NA  
Network Clock is the network-derived clock for SRTS.  
ꢇꢅ  
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