PMC-Sierra, Inc.
PM6541 E1XC-EVBD
TELECOM STANDARD PRODUCT
PMC-930917
ISSUE 1
E1XC EVALUATION DAUGHTERBOARD
2
3
0010
Normal Mode
Externally applied 4.096
MHz. clock is used to
generate the 2.048 MHz
output clock and 8 kHz
frame pulse.
Operates as above.
0011
Normal Mode
Normal Mode
Operates as above.
Generates the CEPT (ST-
BUS) timing signals locked
to the 8 kHz input signal
(C8KB)
DEFAULT
CONFIG
4
5
0100
Divide-1 Mode:
Externally applied 4.096
MHz. clock and 8 kHz.
frame pulse, properly phase
related, are used to
generate the 2.048 MHz
output clock.
Divides the CVB input
signal by 193.The divided
output is connected to
DPLL #2
0101
Divide-1 Mode
Single Clock-1 Mode:
Operates as above
Provides the CEPT/ST-BUS
compatible timing signals
locked to an 8 kHz. internal
signal provided by DPLL
#1.
6
7
8
9
0110
0111
1000
1001
Divide-1 Mode
Divide-1 Mode
Normal Mode
Normal Mode
Same as 'mode 2'
Single Clock-1 Mode
Same as 'mode 0'
F0B becomes an input.
DPLL #2 provides the ST-
BUS signals locked onto
F0B input only if it is 16
kHz.
10
11
1010
1011
Normal Mode
Normal Mode
Same as 'mode 2'
Free Run Mode
Provides the CEPT/ST-BUS
compatible timing and
framing signals with no
external inputs other than
the master clock.
20
PMC [ PMC-SIERRA, INC ]
