PMC-Sierra, Inc.
PM6541 E1XC-EVBD
TELECOM STANDARD PRODUCT
PMC-930917
ISSUE 1
E1XC EVALUATION DAUGHTERBOARD
C048H
C049H
C04AH
C04BH
C04CH
C04DH
C04EH
C04FH
C059H
C05DH
C148H
PMON TSB Control/Status
PMON TSB FER Count
C149H
C14AH
C14BH
C14CH
C14DH
C14EH
C14FH
C159H
C15DH
PMON TSB FEBE Count (LSB)
PMON TSB FEBE Count (MSB)
PMON TSB CRC Count (LSB)
PMON TSB CRC Count (MSB)
PMON TSB LCV Count (LSB)
PMON TSB LCV Count (MSB)
RSLC TSB Configuration
RSLC TSB Interrupt Enable/Status
WRITE CYCLE
READ CYCLE
BALE
BE_CLOCK
BA="C0";
BRWB=1
BA °"C0";
BRWB=1
BA="C0";
BRWB=0
BA °"C0";
BRWB=0
BRWB
BA[15:8]
A[7:0]
DOUT
A[7:0]
DOUT
A[7:0]
DIN
A[7:0]
DIN
BAD[7:0]
T1XC_RDB
HCT245 DIR
T1XC_WRB
T1XC_CSB
Figure 4: Decode Logic Waveforms
Clock PLL and DIP Switches
6.3
One Mitel MT8940 provides all clocks necessary to drive the 2048 kbit/s backplane
rate supported by the E1XC. The MT8940 is a dual digital PLL which can provide
timing and synchronization signals for T1 or CEPT transmission links and the ST-
BUS . The first PLL provides the T1 clock (1.544 MHz) synchronized to an input
framing pulse. The second PLL provides CEPT or ST-BUS timing signals
synchronized to an internal or external framing pulse signal. For a more detailed
18
PMC [ PMC-SIERRA, INC ]
