PMC-Sierra, Inc.
PM6541 E1XC-EVBD
TELECOM STANDARD PRODUCT
PMC-930917
ISSUE 1
E1XC EVALUATION DAUGHTERBOARD
description of the device, refer to the datasheet on the MT8940 in the Mitel
Semiconductor Databook.
All outputs of the MT8940 are either brought out to header blocks or routed to the
CSU connector DIP sockets. A single 8-position DIP switch provides control over the
mode of the MT8940 device as well as control over the output clock enables. If the
MT8940 is not used, it can be removed from the daughterboard and its oscillators
can be replaced with 1.544 MHz and 2.048 MHz devices. The PLL oscillator clock
outputs are conveniently brought out to the header strip for use on the
daughterboard.
The mapping of the DIP switches to the MT8940 ports is as follows:
Switch ID
SW1-1
SW1-2
SW1-3
SW1-4
SW1-5
Label
MS0
MS1
MS2
MS3
ENC2
Mapping
MS0 (Mode Select '0')
MS1 (Mode Select '1')
MS2 (Mode Select '2')
MS3 (Mode Select '3')
ENC20 (Active high enable control for pins
C2O and C2OB )
SW1-6
SW1-7
SW1-8
ENCV
ENC4
ENCV (Active high enable control for pins
CV and CVB )
ENC40 (Active high enable control for pins
C4O and C4OB )
Unused
Setting these switches selects the operating mode for the MT8940, as described
below:
Mode # MS[0:3]
DPLL #1 Operating Mode DPLL #2 Operating Mode
0
0000
Normal Mode:
Externally applied 4.096
MHz. clock and 8 kHz.
frame pulse, properly phase
related, are used to
generate the 2.048 MHz
output clock.
Generates the 1.544 MHz
T1 clock synchronized to
the falling edge of the input
framing pulse.
1
0001
Normal Mode
Normal Mode:
Operates as above.
Generates the CEPT (ST-
BUS) timing signals locked
to the 8 kHz input signal
(C8KB)
19
PMC [ PMC-SIERRA, INC ]
