PMC-Sierra, Inc.
PM6541 E1XC-EVBD
TELECOM STANDARD PRODUCT
PMC-930917
ISSUE 1
E1XC EVALUATION DAUGHTERBOARD
J21
J24
BEXTCLK
C2M
C1M5
BEXTFP
GFP
J20
E-1
E-1
Transmit
Interface
Transmit
TAP
Interface
BTPCM
BTPCM
TAP
TAN
BTSIG
BTFP
BTSIG
BTFP
C
U
S
T
O
M
E
R
"N
E
T
W
O
R
K"
TAN
BTCLK
BTCLK
BRFPI
BRCLK
BRFPI
BRCLK
RAS
BRPCM
BRSIG
BRFPO
RCLKO
RAS
REF
BRPCM
BRSIG
BRFPO
E-1
Receive
Interface
E-1
Receive
Interface
RCLKO
RFP
REF
RFP
GFP
BEXTFP
J19
J22
RFP
J30
C1M5
C2M
BEXTCLK
J23
Figure 5: CSU Circuit Overview
Both E1XCs are connected in a symmetrical fashion and most connections are
completed by installing shorting bar jumpers into the two 16 pin DIP sockets labeled
for the CSU set-up. The remaining unconnected signals are BRCLK, BRFPI, and
BTCLK. By installing jumpers across pins 1 and 2 of each of jumper blocks J19 and
J20, between pins 3 and 4 of each of the jumper blocks J21, J22, J23, J24, and
between pin 2 and 3 of jumper block J30, a "CSU" like application can be
implemented where the 2.048 MHz clock for the backplane between the two E1XC
devices is provided by the MT8940, which in turn is locked to the recovered clock
provided by E1XC #1. Bits 1 and 2 of SW1 must be closed; the remaining bits
23
PMC [ PMC-SIERRA, INC ]
