PMC-Sierra, Inc.
PM6541 E1XC-EVBD
TELECOM STANDARD PRODUCT
PMC-930917
ISSUE 1
E1XC EVALUATION DAUGHTERBOARD
multiplexed address/data bus. All motherboard signals from the 96-pin DIN
connector have been tied through SIPs to insure proper standalone operation. The
standard techniques outlined in the EVMB datasheet for implementing the decoding
and buffering has been followed.
6.2
Decode Logic
The decode logic provides the address mapping of all internal registers of both
E1XC's as well as providing generation of the required RDB and WRB signals.
Again the implementation of the decode logic has followed the techniques outlined
in the EVMB datasheet. E1XC #1 (EAST) is mapped starting at address C000H and
E1XC #2 (WEST) is mapped starting at address C100H. Two unused chip selects,
active for address ranges C200-C2FFH and C300-C3FFH, are available for use on
the prototype section. The full register map is given below:
East E1XC
C000H
C001H
C002H
C003H
C004H
C005H
C006H
C007H
C008H
C009H
C00AH
C00BH
C00CH
C00DH
C00EH
C00FH
C010H
C011H
C012H
C013H
C014H
C015H
C016H
C017H
C018H
West E1XC
C100H
C101H
C102H
C103H
C104H
C105H
C106H
C107H
C108H
C109H
C10AH
C10BH
C10CH
C10DH
C10EH
C10FH
C110H
C111H
C112H
C113H
C114H
C115H
C116H
C117H
C118H
Description
E1XC Receive Options
E1XC Receive Backplane Options
E1XC Datalink Options
E1XC Receive Interface Configuration
E1XC Transmit Interface Configuration
E1XC Transmit Backplane Options
E1XC Transmit Framing Options
E1XC Transmit Timing Options
E1XC Master Interrupt Source
E1XC Receive TS0 Data Link Enables
E1XC Master Diagnostics
E1XC Master Test
E1XC Revision/Chip ID
E1XC Master Reset
E1XC Phase Status Word (LSB)
E1XC Phase Status Word (MSB)
CDRC TSB Configuration
CDRC TSB Interrupt Enable
CDRC TSB Interrupt Status
Alternate Loss of Signal
XPLS TSB Line Length Configuration
XPLS TSB Control/Status
XPLS TSB CODE Indirect Address
XPLS TSB CODE Indirect Data
DJAT TSB Interrupt Status
16
PMC [ PMC-SIERRA, INC ]
