PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
11.1 Internal Registers
Register 00H: E1XC Receive Options
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WORDERR
CNTNFAS
ELSTBYP
TRSLIP
0
0
0
0
0
0
0
0
SRPCM
SRSMFP
SRCMFP
TRKEN
This register allows software to configure the receive functions of the E1XC.
WORDERR:
The WORDERR bit determines how frame alignment signal (FAS) errors are
reported. When WORDERR is logic 1, one or more errors in the seven bit
FAS word results in a single framing error count. When WORDERR is logic 0,
each error in a FAS word results in a single framing error count.
CNTNFAS:
When the CNTNFAS bit is a logic 1, a zero in bit 2 of time slot 0 of non-frame
alignment signal (NFAS) frames results in an increment of the framing error
count. If WORDERR is also a logic 1, the word is defined as the eight bits
comprising the FAS pattern and bit 2 of time slot 0 of the next NFAS frame.
When the CNTNFAS bit is a logic 0, only errors in the FAS affect the framing
error count.
ELSTBYP:
The ELSTBYP bit allows the Elastic Store (ELST) block to be bypassed,
eliminating the one frame delay incurred through the ELST. When set to logic
1, the received data and clock inputs to ELST are internally routed directly to
the ELST outputs.
TRSLIP:
The TRSLIP bit allows the ELST block to be used to measure, through SLIP
indications, the frequency difference between the recovered receive line clock
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
66
PMC [ PMC-SIERRA, INC ]
