PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
and the transmit clock driving the TRAN block when the ELST is bypassed.
When TRSLIP is set to logic 1, the transmit clock input to TRAN is internally
substituted for the BRCLK input to the system side of the ELST. When
TRSLIP is set to logic 0, the BRCLK input is routed to the system side of the
ELST. The TRSLIP bit should only be set if ELSTBYP is set to logic 1.
SRPCM:
The SRPCM bit selects the output signal seen on the multifunction output
RPCM/ RDPCM. When set to logic 1, the multifunction output becomes
RPCM, the undecoded PCM output from the Clock and Data Recovery
(CDRC) block. When SRPCM is set to logic 0, the multifunction output
becomes RDPCM, the HDB3-decoded PCM output from the CDRC block.
SRSMFP, SRCMFP:
The SRSMFP and SRCMFP bits select the output signal seen on the output
RFP. The following table summarizes the four configurations:
SRSMFP SRCMFP Result
0
0
Receive frame pulse output:
RFP pulses high for 1 RCLKO cycle during bit 1
of each 256-bit frame, indicating the frame
alignment of the RDPCM/RPCM data stream.
0
1
Receive CRC multiframe output:
RFP pulses high for 1 RCLKO cycle during bit 1
of frame 1 of every 16 frame CRC multiframe,
indicating the CRC multiframe alignment of the
RDPCM/RPCM data stream. (Even when CRC
multiframing is disabled, the RFP output
continues to indicate the position of bit 1 of the
th
FAS frame every 16 frame.)
1
0
Receive signalling multiframe output:
RFP pulses high for 1 RCLKO cycle during bit 1
of frame 1 of the 16 frame signalling multiframe,
indicating the signalling multiframe alignment of
the RDPCM/RPCM data stream. (Even when
signalling multiframing is disabled, the RFP
output continues to indicate the position of bit 1
th
of every 16 frame.)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
67
PMC [ PMC-SIERRA, INC ]
