PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
configuration, the Timing Options OCLKSEL[1:0] bits should be programmed to
01, the TCLKISEL bit should be programmed to 1, and the SMCLKO bit should
be programmed to 1. Also, the DJAT SYNC and LIMIT bits should be disabled
and the CENT bit enabled. This provides the maximum phase difference
between the input clock and the gapped output clock of 40UI.The maximum jitter
and wander between the two clocks is 8UIpp.
14.10.4
AlternateTCLKO Reference Application
In applications where TCLKO is referenced to an Nx8 kHz clock source applied
on TCLKI, DJAT can be configured by programming the output clock divisor, N2,
to FFH and the input clock divisor, N1, to the value (N-1). The resultant input
clocks to the phase comparator are both 8kHz. The DJAT SYNC and LIMIT bits
should be disabled in this configuration.
14.10.5
Changing the JitterTransfer Function
The DJAT phase lock loop has a single order low pass jitter transfer function. By
default, the corner frequency is 8.8 Hz. The corner may be moved by the
appropriate selection of clock divisors:
2048 kHz
f =
c
(
)
π
+
1536 N2 1
where
f =
c
corner frequency
N2=
value in the Output Clock Divisor Control register
Ensure the Reference Clock Divisor Control value (N1) is also modified to satisfy:
fREF 2048
kHz
+
+
N2 1
N1 1
14.11 Using the Performance Monitor Counter Values
All PMON block event counters are of sufficient length so that the probability of
-3
counter saturation over a one second interval at a 10 BER is less than 0.001%.
The odds of any one of the counters saturating during a one second sampling
interval go up as the BER increases. At some point, the probability of counter
saturation reaches 50%. This point varies, depending upon the framing format
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
223
PMC [ PMC-SIERRA, INC ]
