PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Figure 26
- XFDL Underrun Sequence
Serial Data
inserted into
ESF FDL
Flag D1
D2
D3 Abort Flag D1
D2
TDLINT
TDLUDR
D[7:0]
INTE D1 D2
D3
UDR
INTE
INTE D1 D2
D3
D4
This diagram shows the relationship between XFDL inputs and outputs in the
case of an underrun error. An underrun error occurs if the XFDL finishes
transmitting the current message byte before the processor writes the next byte
into the XFDL Transmit Data Register; that is, the processor fails to write data to
the XFDL in time. In this example, data is not written to the XFDL within the
time-out period after TDLINT goes high at the beginning of the transmission of
byte D3. The TDLUDR interrupt becomes active at this point, and an abort,
followed by a flag, is sent out on the data link. Meanwhile, the processor must
clear the TDLUDR interrupt by setting the UDR bit in the XFDL Interrupt Status
Register to logic 0. The TDLINT interrupt should also be disabled at this time by
setting the INTE bit in the XFDL Configuration Register to logic 0. The data
frame can then be restarted as usual, by setting the INTE bit logic to 1.
Transmission of the frame then proceeds normally.
14.4 Using the Loopback Modes
The E1XC provides four loopback modes to aid in network and system
diagnostics.The network loopbacks (PAYLOAD and LINE) can be initiated at any
time via the µP interface, but are usually initiated once an inband loopback
activate code is detected.The system loopbacks (Diagnostic DIGITAL and
METALLIC) can be initiated at any time by the system via the µP interface to
check the path of system data through the transceiver.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
206
PMC [ PMC-SIERRA, INC ]
