欢迎访问ic37.com |
会员登录 免费注册
发布采购

PM6341-QI 参数 Datasheet PDF下载

PM6341-QI图片预览
型号: PM6341-QI
PDF下载: 下载PDF文件 查看货源
内容描述: E1成帧器/收发器 [E1 FRAMER/TRANSCEIVER]
分类和应用: PC
文件页数/大小: 272 页 / 902 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM6341-QI的Datasheet PDF文件第158页浏览型号PM6341-QI的Datasheet PDF文件第159页浏览型号PM6341-QI的Datasheet PDF文件第160页浏览型号PM6341-QI的Datasheet PDF文件第161页浏览型号PM6341-QI的Datasheet PDF文件第163页浏览型号PM6341-QI的Datasheet PDF文件第164页浏览型号PM6341-QI的Datasheet PDF文件第165页浏览型号PM6341-QI的Datasheet PDF文件第166页  
PM6341 E1XC  
DATA SHEET  
PMC-910419  
ISSUE 8  
E1 FRAMER/TRANSCEIVER  
Register 34H: XFDL Block Configuration  
Bit  
Type  
Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Unused  
Unused  
Unused  
EOM  
X
X
X
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
INTE  
ABT  
CRC  
EN  
EN:  
The enable bit (EN) controls the overall operation of the XFDL block. When  
the EN bit is set to a logic 1, the XDFL block is enabled and flag sequences  
are sent until data is written into the Transmit Data register. When the EN bit  
is set to logic 0, the XFDL block is disabled.  
CRC:  
The CRC enable bit controls the generation of the ITU-T-CRC frame check  
sequence (FCS). Setting the CRC bit to logic 1 enables the ITU-T-CRC  
generator and the appends the 16 bit FCS to the end of each message.  
When the CRC bit is set to logic 0, the FCS is not appended to the end of the  
message. The CRC type used is the ITU-T-CRC with generator polynomial =  
16  
12  
5
x
+ x +x + 1.The high order bit of the FCS word is transmitted first.  
ABT:  
The Abort (ABT) bit controls the sending of the 7 consecutive ones HDLC  
abort code. Setting the ABT bit to a logic 1 causes the 11111110 code to be  
transmitted after the last byte from the Transmit Data Register is transmitted.  
Aborts are continuously sent until this bit is reset to a logic 0.  
INTE:  
The INTE bit enables the generation of an interrupt via the TDLINT output.  
Setting the INTE bit to logic 1 enables the generation of an interrupt; setting  
INTE to logic 0 disables the generation of an interrupt. If the TDLINTE bit is  
also set to logic 1 in the Datalink Options register, the interrupt generated on  
the TDLINT output is also generated on the microprocessor INTB pin.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
146  
 复制成功!