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PM6341-QI 参数 Datasheet PDF下载

PM6341-QI图片预览
型号: PM6341-QI
PDF下载: 下载PDF文件 查看货源
内容描述: E1成帧器/收发器 [E1 FRAMER/TRANSCEIVER]
分类和应用: PC
文件页数/大小: 272 页 / 902 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM6341 E1XC  
DATA SHEET  
PMC-910419  
ISSUE 8  
E1 FRAMER/TRANSCEIVER  
Register 35H: XFDL Block Interrupt Status  
Bit  
Type  
Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Unused  
Unused  
Unused  
Unused  
Unused  
Unused  
INT  
X
X
X
X
X
X
X
0
R
R/W  
UDR  
INT:  
The INT bit indicates when the XFDL block is ready to accept a new data byte  
for transmission.The INT bit is set to a logic 1 when the previous byte in the  
Transmit Data register has been loaded into the parallel to serial converter  
and a new byte can be written into the Transmit Data register.The INT bit is  
set to a logic 0 while new data is in the Transmit Data register.The INT bit is  
not disabled by the INTE bit in the configuration register.  
UDR:  
The UDR bit indicates when the XFDL block has underrun the data in the  
Transmit Data register.The UDR bit is set to a logic 1 if the parallel to serial  
conversion of the last byte in the Transmit Data register has completed before  
the new byte was written into the Transmit Data register. Once an underrun  
has occurred, the XFDL transmits an ABORT, followed by a flag, and waits to  
transmit the next valid data byte. If the UDR bit is still set after the  
transmission of the flag the XFDL will continuously transmit the all-ones idle  
pattern. The UDR bit can only be cleared by writing a logic 0 to the UDR bit  
position in this register.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
148  
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