PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
10.9 Receive Phy Interface (RXPHY)
The S/UNI-2488 receive system interface can be configured for ATM or POS mode. When
configured for ATM applications, the system interface provides a 32-bit Receive UTOPIA Level 3
compatible bus to allow the transfer of ATM cells between the ATM layer device and the S/UNI-
2488. When configured for POS applications, the system interface provides either a 32-bit POS-
PHY Level 3 compliant bus for the transfer of ATM cells and data packets between the link layer
device and the S/UNI-2488. The link layer device can implement various protocols, including
PPP and HDLC.
10.9.1 Receive UTOPIA Level 3 Interface
The UTOPIA Level 3 compliant interface accepts a read clock (RFCLK) and read enable signal
(RENB). The interface indicates the start of a cell (RSOC) when data is read from the receive
FIFO (using the rising edges of RFCLK). The RCA signal indicates when a cell is available for
transfer on the receive data bus RDAT[31:0]. The RPRTY signal reports the parity on the
RDAT[31:0] bus (selectable as odd or even parity). This interface also indicates FIFO overruns
via a maskable interrupt and register bits. Read accesses while RCA is deasserted will output
invalid data.
10.9.2 Receive POS-PHY Level 3
The interface accepts a read clock (RFCLK) and read enable signal (RENB) when data is read
from the receive FIFO (using the rising edge of the RFCLK). The start of packet RSOP marks the
first byte of receive packet data on the RDAT[31:0]. The RPRTY signal determine the parity on
the RDAT[31:0] bus (selectable as odd or even parity). The end of a packet is indicated by the
REOP signal. Signal RERR is provided to indicate that an error in the received packet has
occurred (the error may have several causes include an abort sequence or an FCS error). The
RVAL signal is used to indicate when RSOP, REOP, RERR and RDAT[31:0] are valid. Read
accesses while RVAL is logic 0 are ignored and will output invalid data. RSX indicates the start of
a transfer and marks the clock cycle where the in-band channel address is given on the RDAT
bus. The RXPHY performs the polling procedure to select which PHY address is serviced.
10.10 Transmit Line Interface
The Transmit Line Interface allows the S/UNI-2488 to directly interface with optical modules
(ODLs) or other medium interfaces. This block performs clock synthesis and performs parallel to
serial conversion of the incoming outgoing 2488.32 Mbit/s data stream.
The transmit clock is synthesized from a 155.52. MHz reference. The transfer function yields a
typical low pass corner of TBD MHz above which reference jitter is attenuated at TBD dB per
octave. The design of the loop filter and PLL is optimized for minimum intrinsic jitter. With a jitter
free 155.52MHz reference, the intrinsic jitter is typically less than TBD UI RMS when measured
using a high pass filter with a TBD cutoff frequency.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
71
PMC [ PMC-SIERRA, INC ]
