PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
The values of ALPHA and DELTA determine the robustness of the delineation process. ALPHA
determines the robustness against false misalignments due to bit errors. DELTA determines the
robustness against false delineation in the synchronization process. ALPHA is chosen to be 7
and DELTA is chosen to be 6. These values result in an average time to delineation of 2 µs for
the STS-48c (STM-16c) rate.
10.7.2 ATM Descrambler
The self-synchronous descrambler operates on the 48 byte cell payload only. The circuitry
43
descrambles the information field using the x + 1 polynomial. The descrambler is disabled for
the duration of the header and HCS fields and may optionally be disabled for the payload.
10.7.3 ATM Cell Filter and HCS Verification
Cells are filtered (or dropped) based on HCS errors and/or a cell header pattern. Cell filtering is
optional and is enabled through the RCFP registers. Cells are passed to the receive FIFO while
the cell delineation state machine is in the SYNC state as described above. When both filtering
and HCS checking are enabled, cells are dropped if uncorrectable HCS errors are detected, or if
the corrected header contents match the pattern contained in the RCFP Idle Cell Header and
Mask register. Idle cell filtering is accomplished by writing the appropriate cell header pattern into
the RCFP Idle Cell Header and Mask Pattern register. Idle/Unassigned cells are assumed to
contain the all zeros pattern in the VCI and VPI fields. The RCFP Idle Cell Header and Mask
register allows filtering control over the contents of the GFC, PTI, and CLP fields of the header.
The HCS is a CRC-8 calculation over the first 4 octets of the ATM cell header. The RCFP block
8
2
6
4
verifies the received HCS using the polynomial, x + x + x + 1. The coset polynomial, x + x +
2
x + 1, is added (modulo 2) to the received HCS octet before comparison with the calculated
result. ATM Performance Monitor
The Performance Monitor consists of two 16-bit saturating HCS error event counters and a 32-bit
saturating receive cell counter. The first error counter accumulates uncorrectable HCS errors. A
32-bit receive cell counter counts all cells written into the receive FIFO. Filtered cells are not
counted.
Each counter may be read through the microprocessor interface. Circuitry is provided to latch
these counters so that their values can be read while simultaneously resetting the internal
counters to 0 or 1, if appropriate, so that a new period of accumulation can begin without loss of
any events. It is intended that the counter be polled at least once per second so as not to miss
any counted events.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
67
PMC [ PMC-SIERRA, INC ]
