PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
The RCFP monitors the packets for both minimum and maximum length errors. When a packet
size is smaller than MINPL[7:0], the packet is marked with an error but still written into the FIFO.
Malformed packets, that is packets that do not at least contain four bytes, are discarded and will
be counted as a minimum packet size violation. When the packet size exceeds MAXPL[16:0] the
packet is marked with an error and the bytes beyond the maximum count are discarded.
10.8 Receive Scalable Data Queue (RXSDQ)
The RXSDQ provides a FIFO to separate the line-side timing from the higher layer ATM/POS link
layer timing. The RXSDQ has two modes of operations, ATM and POS.
10.8.1 Receive ATM FIFO
The RXSDQ is responsible for holding up to 48 cells until they are read by the Receive System
Interface.
Receive FIFO management functions include filling the receive FIFO, indicating when cells are
available to be read from the receive FIFO, maintaining the receive FIFO read and write pointers,
and detecting FIFO overrun conditions. Upon detection of an overrun, the FIFO discards the
current cell and discards the incoming cells until there is room in the FIFO. FIFO overruns are
indicated through a maskable interrupt and register bit and are considered a system error.
10.8.2 Receive POS FIFO
The RXSDQ contains 48 sixteen byte blocks for FIFO storage, along with management circuitry
for reading and writing the FIFO. The receive FIFO provides for the separation of the physical
layer timing from the system timing.
Receive FIFO management functions include filling the receive FIFO, indicating when packets or
bytes are available to be read from the receive FIFO, maintaining the receive FIFO read and write
pointers, and detecting FIFO overrun and underrun conditions. Upon detection of an overrun, the
FIFO aborts the current packet and discards the current incoming bytes until there is room in the
FIFO. Once enough room is available, as defined by the BT[7:0] register bit settings, the RXSDQ
will wait for the next start of packet before writing any data into the FIFO. FIFO overruns are
indicated through a maskable interrupt and register bit and are considered a system error. A
FIFO underrun is caused when the System Interface tries to read more data words while the
FIFO is empty. This action will be detected and reported through the FUDRI interrupt, but it is not
considered a system error. The system will continue to operate normally. In that situation, RVAL
can be used by the Link Layer device to find out if valid or invalid data is provided on the System
Interface.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
70
PMC [ PMC-SIERRA, INC ]
