PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
9.2
Clocks and Alarms (7)
Pin Name
Type
Pin
No.
Function
PGMRCLK
Output
AK25 The programmable receive clock (PGMRCLK) signal
provides timing reference for the receive line interface.
PGMRCLK is a divided version of the recovered clock. When
PGMRCLKSEL register bit is set low, PGMRCLK is a nominal
19.44 MHz, 50% duty cycle clock. When PGMRCLKSEL
register bit is set to high, PGMRCLK is a nominal 8 KHz, 50%
duty cycle clock.
The PGMRCLK output can be disabled and held low by
programming the PGMRCLKEN bit in the SRLI PGM Clock
Configuration register.
RCLK
Output
AG23 The receive clock (RCLK) signal provides timing reference
for the receive interface.
RCLK is a nominal 77.76 MHz 50% duty cycle clock. The
RCLK output can be disabled and held low by programming
the RCLKEN bit in the SRLI Clock Configuration register.
OOF and SALM are updated on the rising edge of RCLK.
The programmable transmit clock (PGMTCLK) signal
PGMTCLK
Output
AH23
provides timing reference for the transmit line interface.
PGMTCLK is a divided version of the recovered clock. When
PGMTCLKSEL register bit is set low, PGMTCLK is a nominal
19.44 MHz, 50% duty cycle clock. When PGMTCLKSEL
register bit is set to high, PGMTCLK is a nominal 8 KHz, 50%
duty cycle clock.
The PGMTCLK output can be disabled and held low by
programming the PGMTCLKEN bit in the STLI PGM Clock
Configuration register.
TCLK
Output
AJ24
The transmit clock (TCLK) signal provides timing reference
for the transmit interface.
TCLK is a nominal 77.76MHz 50% duty cycle clock. The
TCLK output can be disabled and held low by programming
the TCLKEN bit in the STLI PGM Clock Configuration register.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
21
PMC [ PMC-SIERRA, INC ]
