PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
9
SDPIN DESCRIPTION
9.1
Serial Line Side Interface Signals (7)
Pin Name
Type
Pin
No.
Function
REFCLK+
REFCLK-
Differential AK10
PECL Input AK9
The differential reference clock inputs (REFCLK+/-) provides a
jitter-free 155.52 MHz reference clock for both the clock
recovery and the clock synthesis circuits. The 8kHz frame
pulse, APSIFP is sampled upon a rising edge transition of
REFCLK+/- (i.e. APSIFP is phase-synchronous with REFCLK+/-
). APSOFP is updated upon a rising edge transition of
REFCLK+/- (i.e. APSOFP is phase-synchronous with
REFCLK+/-).
Please refer to the Operation section for a discussion of PECL
interfacing issues.
RXD+
RXD-
Differential AK16
PECL Input AK15
The receive differential data PECL inputs (RXD+/-) contain the
NRZ bit serial receive stream. The receive clock is recovered
from the RXD+/- bit stream.
Please refer to the Operation section for a discussion of PECL
interfacing issues.
SD
TTL
Input
AH24
The receive signal detect TTL input (SD) indicates the
presence of valid receive signal power from the Optical Physical
Medium Dependent Device. A logic high indicates the presence
of valid data. A logic low indicates a loss of signal.
Please refer to the Operation section for a discussion of
interfacing issues
TXD+
TXD-
Differential AK13
PECL Output AK12
The transmit differential data PECL outputs (TXD+/-) contain
the 2488.32 Mbit/s transmit stream. The TXD+/- outputs are
driven using the synthesized clock from the CSU.
Please refer to the Operation section for a discussion of PECL
interfacing issues.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
20
PMC [ PMC-SIERRA, INC ]
