PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
When used to implement an ATM UNI or NNI, ATM cells are written to an internal 8 cell FIFO
using a 32-bit wide UTOPIA Level 3 (clocked up to 104 MHz) datapath interface. Idle/unassigned
cells are automatically inserted when the internal FIFO contains less than one complete cell. The
S/UNI-2488 provides generation of the header check sequence and scrambles the payload of the
ATM cells. Each of these transmit ATM cell processing functions can be enabled or bypassed.
When used to implement a Packet over SONET/SDH link, the S/UNI-2488 inserts POS frames
into the SONET/SDH synchronous payload envelope. Packets to be transmitted are written into a
256-byte FIFO through a 32-bit SATURN POS-PHY Level 3 (clocked up to 104 MHz) system side
interface. POS frames are built by inserting the flags, control escape characters and the FCS
fields. Either the CRC-CCITT or CRC-32 can be computed and added to the frame. Several
counters are provided for performance monitoring.
No line rate clocks are required directly by the S/UNI-2488 as it synthesizes the transmit clock
and recovers the receive clock using a 155.52 MHz reference clock. The S/UNI-2488 outputs a
differential PECL line data (TXD+/-).
The S/UNI-2488 is configured, controlled and monitored via a generic 16-bit microprocessor bus
interface. The S/UNI-2488 also provides a standard 5 signal IEEE 1149.1 JTAG test port for
boundary scan board test purposes.
The S/UNI-2488 is implemented in low power, +1.8 Volt, CMOS technology. It has TTL
compatible digital inputs and TTL/CMOS compatible digital outputs. High speed inputs and
outputs support 3.3V compatible pseudo-ECL (PECL). The S/UNI-2488 is packaged in a 416 pin
UBGA package.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
18
PMC [ PMC-SIERRA, INC ]
