欢迎访问ic37.com |
会员登录 免费注册
发布采购

PM5381 参数 Datasheet PDF下载

PM5381图片预览
型号: PM5381
PDF下载: 下载PDF文件 查看货源
内容描述: SATURN用户网络接口,用于2488 Mbit / s的 [SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S]
分类和应用: 网络接口
文件页数/大小: 487 页 / 2424 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM5381的Datasheet PDF文件第137页浏览型号PM5381的Datasheet PDF文件第138页浏览型号PM5381的Datasheet PDF文件第139页浏览型号PM5381的Datasheet PDF文件第140页浏览型号PM5381的Datasheet PDF文件第142页浏览型号PM5381的Datasheet PDF文件第143页浏览型号PM5381的Datasheet PDF文件第144页浏览型号PM5381的Datasheet PDF文件第145页  
PMC-Sierra, Inc.  
PRELIMINARY  
PM5381 S/UNI-2488  
DATASHEET  
PMC-2000489  
ISSUE 1  
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S  
is generated upon assertion of the FIFO_UNDF_I register bit. When FIFO_UNDF_EN is set  
low, a change in the FIFO_UNDF_I status does not generate an interrupt.  
FIFO_OVRF_EN:  
The FIFO Overflow Enable bit connects the FIFO_OVRF_I status bit to the ECBI_INTB pin of  
the RCS_2488. When FIFO_OVRF_EN is set to logic one, an interrupt on the ECBI_INTB is  
generated upon assertion of the FIFO_OVRF_I register bit. When FIFO_OVRF_EN is set  
low, a change in the FIFO_OVRF_I status does not generate an interrupt.  
PRBS_ERR_EN:  
The PRBS Error Enable bit connects the PRBS_ERR_I status bit to the ECBI_INTB pin of the  
RCS_2488. When PRBS_ERR_EN is set to logic one, an interrupt on the ECBI_INTB is  
generated upon assertion of the PRBS_ERR_I register bit. When PRBS_ERR_EN is set low,  
a change in the PRBS_ERR_I status does not generate an interrupt.  
PRBS_SYNC_EN:  
The PRBS Synchronized Enable bit connects the PRBS_SYNC_I status bit to the ECBI_INTB  
pin of the RCS_2488. When PRBS_SYNC_EN is set to logic one, an interrupt on the  
ECBI_INTB is generated upon assertion of the PRBS_SYNC_I register bit. When  
PRBS_SYNC_EN is set low, a change in the PRBS_SYNC_I status does not generate an  
interrupt.  
ROOL_I:  
The recovered reference out of lock status indicates the clock recovery phase locked loop is  
unable to lock to the reference clock on REFCLK. ROOL_I is a logic one if the divided down  
synthesized clock frequency is not within 488 ppm of the REFCLK frequency. At startup,  
ROOL_I may remain at logic 1 for several hundred millisecond while the PLL obtains lock.  
This bit is only cleared by over-writing with a ‘1’.  
DOOL_I:  
The recovered data out of lock status indicates the clock recovery phase locked loop is  
unable to recover and lock to the input data stream. DOOL_I is a logic one if the divided  
down recovered clock frequency is not within 488 ppm of the REFCLK frequency of if no  
transitions have occurred on the RXD input for more than LOS_COUNT[4:0] bits. This bit is  
only cleared by over-writing with a ‘1’.  
LOS_I:  
The loss of signal status indicates the receive signal is lost or at least LOS_COUNT[4:0]  
consecutive ones or zeros have been received. LOS_I is a logic zero if the SDI input is high  
or less than LOS_COUNT[4:0] consecutive ones or zeros have been received. LOS_I is a  
logic one if the SDI input is low or LOS_COUNT[4:0] consecutive ones or zeros have been  
received. This bit is only cleared by over-writing with a ‘1’.  
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use  
120  
 复制成功!