S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
10.22.5Loss of Signal
The Loss of Signal Block monitors the scrambled data of the receive stream for the absence of
1's or 0’s. When 20 ± 3 µs of all zeros patterns or all ones patterns are detected, a loss of signal
(LOS) is declared. Loss of signal is cleared when two valid framing words are detected and
during the intervening time, no loss of signal condition is detected. The APS path stream is
forced to all ones (PAIS) when LOS occurs.
10.22.6Loss of Frame
The Loss of Frame Block monitors the in-frame / out-of-frame status of the Framer Block. A
loss of frame (LOF) is declared when an out-of-frame (OOF) condition persists for 3 ms. The
LOF is cleared when an in-frame condition persists for a period of 3 ms. To provide for
intermittent out-of-frame (or in-frame) conditions, the 3 ms timer is not reset to zero until an in-
frame (or out-of-frame) condition persists for 3 ms. The APS path stream is forced to all ones
(PAIS) when OOF or LOF occurs.
10.23 Channel Cross Connect
The Channel Cross Connect allows channels to exchange path information with other channels
as well as exchange path information with the APS serial interface. For all configurations, the
transmit and receive path processors (RPOP and TPOP) of a given channel are a matched set
and exchange path FEBE and RDI information.
In the transmit direction, the cross connect allows two channels to transmit identical path
information (bridge) and/or allow channels to transmit receive APS path data streams
(protection channel function).
In the receive direction, the cross connect allows a receive path processor (RPOP) to select
between receive channels (select between working and protection channels) or select between
receive channels and APS path data streams (select between working and protection channels).
10.24 JTAG Test Access Port
The JTAG Test Access Port block provides JTAG support for boundary scan. The standard
JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The
S/UNI-8x155 identification code is 0x153820CD hexadecimal.
10.25 Microprocessor Interface
The microprocessor interface block provides normal and test mode registers, and the logic
required to connect to the microprocessor interface. The normal mode registers are required for
normal operation, and test mode registers are used to enhance the testability of the S/UNI-
8x155. In the following section every register is documented and identified using the register
number.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
97
PMC [ PMC-SIERRA, INC ]
