S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
9.5 Transmit ATM (UTOPIA) and Packet over SONET/SDH (POS)
System Interface
Pin Name
Type
Pin
Function
No.
POS_
ATMB
Input
AJ20
The physical layer select (POS_ATMB) pin selects between
the ATM and Packet over SONET/SDH modes of operation.
When tied low, the device implements an UTOPIA Level 3
interface. When tied high, the device implements a POS-
PHY Level 3 interface.
This pin affects SONET/SDH mapping as well as the pin
definitions of the system interface bus.
TFCLK
Input
R27
The UTOPIA transmit FIFO write clock (TFCLK) is used to
write ATM cells to the cell transmit FIFO.
In UTOPIA operation, TFCLK must cycle at a 104 MHz to
60 MHz instantaneous rate, and must be a free running clock
(cannot be gapped).
The POS-PHY transmit FIFO write clock (TFCLK) is used to
write packet data into the packet FIFO.
In POS-PHY operation, TFCLK must cycle at a 104 MHz to
60 MHz instantaneous rate, and must be a free running clock
(cannot be gapped).
Note:
Running this interface below 90MHz might result in limited
device performance with respect to throughput for all
possible packet sizes for both UTOPIA and POS-PHY modes
of operation.
TDAT[0]
TDAT[1]
TDAT[2]
TDAT[3]
TDAT[4]
TDAT[5]
TDAT[6]
TDAT[7]
TDAT[8]
TDAT[9]
TDAT[10]
Input
L30
L29
L28
K31
K30
K29
K28
K27
J31
J30
J29
The UTOPIA transmit cell data (TDAT[31:0]) bus carries the
ATM cell octets that are written to the transmit FIFO.
In UTOPIA operation, the TDAT[31:0] bus is considered valid
only when TENB is simultaneously asserted.
TDAT[31:0] is sampled on the rising edge of TFCLK.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
47
PMC [ PMC-SIERRA, INC ]
