S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
9.3 Clocks and Alarms Signals
Pin Name
Type
Pin
Function
No.
RALRM[0]
RALRM[1]
RALRM[2]
RALRM[3]
RALRM[4]
RALRM[5]
RALRM[6]
RALRM[7]
Output
D17
A15
B15
C15
D15
E15
A14
B14
The receive alarm (RALRM[7:0]) outputs indicates the state
of the receive framing for each channel. RALRM is low if no
receive alarms are active. RALRM is optionally high if line
AIS (LAIS), path AIS (PAIS), line RDI (LRDI), path RDI
(PRDI), enhanced path RDI (PERDI), loss of signal (LOS),
loss of frame (LOF), out of frame (OOF), loss of pointer
(LOP), loss of pointer concatenation (LOPC/AISC), loss of
cell delineation (LCD), signal fail BER (SFBER), signal
degrade BER (SDBER), path trace identification mismatch
(TIM) or path signal label mismatch (PSLM) is detected. The
line error component of RALRM reflects the state of the local
channel when the cross-connect is enabled.RALRM[7:0] are
asynchronous outputs with a minimum period of one RCLK
clock.
RCLK
RFPO
Output
Output
C21
D21
The receive clock (RCLK) provides a timing reference for the
S/UNI-8x155 receive function outputs. RCLK is a 19.44
MHz, 50% duty cycle clock.
The receive frame pulse output (RFPO), when the framing
alignment has been found (the OOF register bit is low), is an
8 kHz signal derived from the receive clock RCLK. RFPO
pulses high for one RCLK cycle every 2430 RCLK cycles.
RFPO is updated on the rising edge of RCLK.
TCLK
TFPO
Output
Output
B21
D20
The transmit clock (TCLK) provides timing for the S/UNI-
8x155 transmit function operation for a channel. TCLK is a
19.44 MHz, 50% duty cycle clock.
The active-high framing position output (TFPO) signal is an 8
kHz signal derived from the transmit clock TCLK. TFPO
pulses high for one TCLK cycle every 2430 TCLK cycles.
TFPO is updated on the rising edge of TCLK.
TFPI
Input
D19
The active high framing position (TFPI) signal is an 8 kHz
timing marker for the transmitter. TFPI is used to align the
SONET/SDH transport frame generated by the S/UNI-8x155
device to a system reference. TFPI should be brought high
for a single TCLK period every 2430 (+/-1) TCLK cycles or a
multiple thereof. TFPI must be tied low if such
synchronization is not required. By design, TFPI has a built-in
+/- 1 cycle tolerance.
TFPI is sampled on the rising edge of TCLK.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
45
PMC [ PMC-SIERRA, INC ]
