S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x0A6 , 0x1A6, 0x2A6, 0x3A6, 0x4A6, 0x5A6, 0x6A6, 0x7A6:
RXFP Receive Initiation Level
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Reserved
Reserved
Reserved
Reserved
RIL[3]
RIL[2]
RIL[1]
RIL[0]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
0
0
1
1
0
0
Reserved:
All reserved bits must be programmed to default values for proper operation.
RIL[3:0]:
The Reception Initiation Level (RIL[3:0]) bits are used to set the minimum number of bytes
that must be available in the FIFO before received packets can be written into it. RIL[3:0]
is only used after a FIFO overrun has been detected and FIFO writes have been suspended.
This avoids restarting the reception of data too quickly after an overrun condition. If the
system does not cause any FIFO overrun, then this register will not be used. RIL[3:0]
breaks the FIFO in 16 sections; for example a value of 0x4 correspond to a FIFO level of 64
bytes. The value of RIL must not be too large in order to prevent repetitive FIFO overruns
and must not be programmed to zero.
Table 11 Receive Initiation Level Values
RIL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
FIFO Fill Level
0
RIL[3:0]
1000
1001
1010
1011
1100
1101
1110
1111
FIFO Fill Level
128
144
160
176
192
208
224
240
16
32
48
64
80
96
112
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
254
PMC [ PMC-SIERRA, INC ]
