S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x064, 0x164, 0x264, 0x364, 0x464, 0x564, 0x664, 0x764:
RXCP Status/Interrupt Status
Bit
Type
R
R
Function
OOCDV
LCDV
Unused
OOCDI
Unused
HCSI
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
R
R
R
R
R
FOVRI
LCDI
LCDI:
The LCDI bit is set high when there is a change in the loss of cell delineation (LCD) state.
This bit is reset immediately after a read to this register.
FOVRI:
The FOVRI bit is set high when an attempt is made to write into the channel buffer when it
is already full. This bit is reset immediately after a read to this register. Continuous over-
writing of the channel buffer results in only one interrupt.
HCSI:
The HCSI bit is set high when an HCS error is detected. This bit is reset immediately after
a read to this register.
OOCDI:
The OOCDI bit is set high when the RXCP enters or exits the SYNC state. The OOCDV
bit indicates whether the RXCP is in the SYNC state or not. The OOCDI bit is reset
immediately after a read to this register.
LCDV:
The LCDV bit gives the Loss of Cell Delineation state. When LCD is high, an out of cell
delineation (OCD) defect has persisted for the number of cells specified in the LCD Count
Threshold register. When LCD is low, no OCD has persisted for the number of cells
specified in the LCD Count Threshold register. The cell time period can be varied by using
the LCDC[7:0] register bits in the RXCP LCD Count Threshold register.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
224
PMC [ PMC-SIERRA, INC ]
