S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x063, 0x163, 0x263, 0x363, 0x463, 0x563, 0x663, 0x763:
RXCP Interrupt Enable and Counter Status
Bit
Type
R
R
Function
XFERI
OVR
Unused
XFERE
OOCDE
HCSE
FOVRE
LCDE
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
LCDE:
The LCDE bit enables the generation of an interrupt due to a change in the LCD state.
When LCDE is set high, the interrupt is enabled.
FOVRE:
The FOVRE bit enables the generation of an interrupt due to a FIFO overrun error
condition. When FOVRE is set high, the interrupt is enabled.
HCSE:
The HCSE bit enables the generation of an interrupt due to the detection an HCS error.
When HCSE is set high, the interrupt is enabled.
OOCDE:
The OOCDE bit enables the generation of an interrupt due to a change in cell delineation
state. When OOCDE is set high, the interrupt is enabled.
XFERE:
The XFERE bit enables the generation of an interrupt when an accumulation interval is
completed and new values are stored in the RXCP Count registers. When XFERE is set
high, the interrupt is enabled.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
222
PMC [ PMC-SIERRA, INC ]
