S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
OVR:
The OVR bit is the overrun status of the RXCP Performance Monitoring Count registers. A
logic one in this bit position indicates that a previous transfer (indicated by XFERI being
logic one) has not been acknowledged before the next accumulation interval has occurred
and that the contents of the RXCP Count registers have been overwritten. OVR is set low
when this register is read.
XFERI:
The XFERI bit indicates that a transfer of RXCP Performance Monitoring Count data has
occurred. A logic one in this bit position indicates that the RXCP Count registers have been
updated. This update is initiated by writing to one of the RXCP Count register locations, to
the S/UNI-8x155 Master Reset and Identity register or the channel Master Interrupt Status
register. XFERI is set low when this register is read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
223
PMC [ PMC-SIERRA, INC ]
