S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x03A, 0x13A, 0x23A, 0x33A, 0x43A, 0x53A, 0x63A, 0x73A:
RPOP Path FEBE LSB
Bit
Type
R
R
R
R
R
R
R
R
Function
PFE[7]
PFE[6]
PFE[5]
PFE[4]
PFE[3]
PFE[2]
PFE[1]
PFE[0]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
Register 0x03B, 0x13B, 0x23B, 0x33B, 0x43B, 0x53B, 0x63B, 0x73B:
RPOP Path FEBE MSB
Bit
Type
R
R
R
R
R
R
R
R
Function
PFE[15]
PFE[14]
PFE[13]
PFE[12]
PFE[11]
PFE[10]
PFE[9]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
PFE[8]
These registers allow path FEBEs to be accumulated.
PFE[15:0]:
Bits PFE[15:0] represent the number of path FEBE errors (individual or block) that have
been detected since the last time the error count was polled. The error count is polled by
writing to either of the RPOP Path BIP-8 Register addresses or to either of the RPOP Path
FEBE Register addresses. Such a write transfers the internally accumulated error count to
the Path FEBE Registers within approximately 7 µs and simultaneously resets the internal
counter to begin a new cycle of error accumulation. This transfer and reset is carried out in
a manner that ensures that coincident events are not lost.
The count can also be polled by writing to the S/UNI-8x155 Master Reset and Identity
register (0x000). Writing to register address 0x000 loads all counter registers in all channels
and APS links.
The count can also be polled by writing to the channel Master Interrupt Status register
(offset 0x07). Writing to register offset 0x07 loads all counter registers in the RSOP, RLOP,
RPOP, SPTB, SSTB, RXCP, TXCP, RXFP, and TXFP blocks of the channel.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
186
PMC [ PMC-SIERRA, INC ]
