S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x038, 0x138, 0x238, 0x338, 0x438, 0x538, 0x638, 0x738:
RPOP Path BIP-8 LSB
Bit
Type
R
R
R
R
R
R
R
R
Function
PBE[7]
PBE[6]
PBE[5]
PBE[4]
PBE[3]
PBE[2]
PBE[1]
PBE[0]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
Register 0x039, 0x139, 0x239, 0x339, 0x439, 0x539, 0x639, 0x739:
RPOP Path BIP-8 MSB
Bit
Type
R
R
R
R
R
R
R
R
Function
PBE[15]
PBE[14]
PBE[13]
PBE[12]
PBE[11]
PBE[10]
PBE[9]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
PBE[8]
These registers allow path BIP-8 errors to be accumulated.
PBE[15:0]:
PBE[15:0] represent the number of B3 errors (individual or block) that have been detected
since the last time the error count was polled. The error count is polled by writing to either
of the RPOP Path BIP-8 Register addresses or to either of the RPOP Path FEBE Register
addresses. Such a write transfers the internally accumulated error count to the Path BIP-8
registers within a maximum of 7 µs and simultaneously resets the internal counter to begin
a new cycle of error accumulation. This transfer and reset is carried out in a manner that
ensures that coincident events are not lost.
The count can also be polled by writing to the S/UNI-8x155 Master Reset and Identity
register (0x000). Writing to register address 0x000 loads all counter registers in all
channels and APS links
The count can also be polled by writing to the channel Master Interrupt Status register
(offset 0x07). Writing to register offset 0x07 loads all counter registers in the RSOP, RLOP,
RPOP, SPTB, SSTB, RXCP, TXCP, RXFP, and TXFP blocks of the channel.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
185
PMC [ PMC-SIERRA, INC ]
