S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x040, 0x140, 0x240, 0x340, 0x440, 0x540, 0x640, 0x740:
TPOP Control/Diagnostic
Bit
Type
Function
Unused
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EPRDIEN
EPRDISRC
PERSIST
Reserved
Reserved
DBIP8
PAIS
For more details refer to the Operation Section of this document.
PAIS:
The PAIS bit controls the insertion of STS path alarm indication signal. When a logic one is
written to this bit position, the complete SPE, and the pointer bytes (H1, H2, and H3) are
overwritten with the all-ones pattern. When a logic zero is written to this bit position, the
pointer bytes and the SPE are processed normally.DBIP8:
The DBIP8 bit controls the insertion of bit errors continuously in the B3 byte. When
DBIP8 is a logic one, the B3 byte is inverted.
EPRDISRC:
The enhanced path receive defect indication alarm source bit (EPRDISRC) controls the
source of RDI input to be inserted onto the G1 byte. See the description in register offset
0x049 for more information on the operation of this register.
EPRDIEN
The enhanced path receive defect indication alarm enable bit (EPRDIEN) controls the use
of 3-bit enhanced RDI mode. See the description in register offset 0x049 for more
information on the operation of this register.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
190
PMC [ PMC-SIERRA, INC ]
