S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x031, 0x131, 0x231, 0x331, 0x431, 0x531, 0x631, 0x731 (EXTD=1):
RPOP Interrupt Status
Bit
Type
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
ERDII
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
R
NOTE: To facilitate additional register mapping, shadow registers have been added to channel
registers offset 0x30, 0x31 and 0x33. These shadow registers are accessed in the same way as
the normal registers.
The EXTD (extend register) bit must be set in register 0x36 to allow switching between
accessing the normal registers and the shadow registers.
This register allows identification and acknowledgment of path level alarm and error event
interrupts.
ERDII:
The ERDII bit is set high when a change is detected in the received enhanced RDI state.
This bit is cleared when the RPOP Interrupt Status register is read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
174
PMC [ PMC-SIERRA, INC ]
