S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x031, 0x131, 0x231, 0x331, 0x431, 0x531, 0x631, 0x731 (EXTD=0):
RPOP Interrupt Status
Bit
Type
R
Function
PSLI
Unused
LOPI
Unused
PAISI
PRDII
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
R
R
R
R
R
BIPEI
FEBEI
NOTE: To facilitate additional register mapping, shadow registers have been added to channel
registers offset 0x30, 0x31 and 0x33. These shadow registers are accessed in the same way as
the normal registers.
The EXTD (extend register) bit must be set in register offset 0x36 to allow switching between
accessing the normal registers and the shadow registers.
This register allows identification and acknowledgment of path level alarm and error event
interrupts.
FEBEI:
The FEBEI bit is the path FEBE interrupt status bit. FEBEI is a logic one when a FEBE
error is detected. This bit is cleared when this register is read.
BIPEI:
The BIPEI bit is the path BIP-8 interrupt status bit. BIPEI is a logic one when a B3 error is
detected. This bit is cleared when this register is read.
PRDII:
The PRDII bit is the path remote defect indication interrupt status bit. PRDII is a logic one
when a change in the path RDI state (PRDI) or the auxiliary path RDI (ARDI) state occurs.
This bit is cleared when this register is read.
PAISI:
The PAISI bit is the path alarm indication signal interrupt status bit. PAISI is a logic one
when a change in the path AIS state occurs. This bit is cleared when this register is read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
172
PMC [ PMC-SIERRA, INC ]
