S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x033, 0x133, 0x233, 0x333, 0x433, 0x533, 0x633, 0x733 (EXTD=0):
RPOP Interrupt Enable
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
PSLE
Reserved
LOPE
Reserved
PAISE
PRDIE
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
BIPEE
FEBEE
NOTE: To facilitate additional register mapping, shadow registers have been added to channel
registers offset 0x30, 0x31 and 0x33. These shadow registers are accessed in the same way as
the normal registers.
The EXTD (extend register) bit must be set in register offset0x36 to allow switching between
accessing the normal registers and the shadow registers.
This register allows interrupt generation to be enabled for path level alarm and error events.
FEBEE:
The FEBEE bit is the interrupt enable for path FEBEs. When FEBEE is a logic one, an
interrupt is generated when a path FEBE is detected.
BIPEE:
The BIPEE bit is the interrupt enable for path BIP-8 errors. When BIPEE is a logic one, an
interrupt is generated when a B3 error is detected.
PRDIE:
The PRDIE bit is the interrupt enable for path RDI. When PRDIE is a logic one, an
interrupt is generated when the path RDI state changes.
PAISE:
The PAISE bit is the interrupt enable for path AIS. When PAISE is a logic one, an interrupt
is generated when the path AIS state changes.
LOPE:
The LOPE bit is the interrupt enable for LOP. When LOPE is a logic one, an interrupt is
generated when the LOP state changes.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
177
PMC [ PMC-SIERRA, INC ]
