S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x030, 0x130, 0x230, 0x330, 0x430, 0x530, 0x630, 0x730 (EXTD=1):
RPOP Status/Control
Bit
Type
R/W
R/W
R/W
R/W
Function
Reserved
IINVCNT
PSL5
Reserved
Unused
ERDIV[2]
ERDIV[1]
ERDIV[0]
Default
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
X
X
X
X
R
R
R
NOTE: To facilitate additional register mapping, shadow registers have been added to channel
registers offset 0x30, 0x31 and 0x33. These shadow registers are accessed in the same way as
the normal registers.
The EXTD (extend register) bit must be set in register offset 0x36 to allow switching between
accessing the normal registers and the shadow registers.
The Status Register is provided at RPOP read address 0, if the extend register (EXTD) bit is set
in register 6.
ERDIV[2:0]:
The ERDIV[2:0] bits reflect the current state of the detected enhanced RDI, (filtered G1 bits
5, 6, & 7).
IINVCNT:
When a logic one is written to the IINVCNT (Intuitive Invalid Pointer Counter) bit, if in the
LOP state 3 x new point resets the inv_point count. If this bit is set to 0 the inv_point count
will not be reset if in the LOP state and 3 x new pointers are detected.
PSL5:
The PSL5 bit controls the filtering of the path signal label byte (C2). When PSL5 is set
high, the PSL is updated when the same value is received for 5 consecutive frames. When
the PSL5 is set low, the PSL is updated when the same value is received for 3 consecutive
frames.
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
171
PMC [ PMC-SIERRA, INC ]
