S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x030, 0x130, 0x230, 0x330, 0x430, 0x530, 0x630, 0x730 (EXTD=0):
RPOP Status/Control
Bit
Type
R/W
Function
Reserved
Unused
LOPV
Unused
PAISV
PRDIV
NEWPTRI
NEWPTRE
Default
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
0
R
R
R
R
R/W
NOTE: To facilitate additional register mapping, shadow registers have been added to channel
registers offset 0x30, 0x31 and 0x33. These shadow registers are accessed in the same way as
the normal registers.
The EXTD (extend register) bit must be set in register offset 0x36 to allow switching between
accessing the normal registers and the shadow registers.
This register allows the status of path level alarms to be monitored.
NEWPTRE:
The NEWPTRE bit is the interrupt enable for the receive new pointer status. When
NEWPTRE is a logic one, an interrupt is generated when the pointer interpreter validates a
new pointer.
NEWPTRI:
The NEWPTRI bit is the receive new pointer interrupt status bit. NEWPTRI is a logic one
when the pointer interpreter has validated a new pointer value (H1, H2). NEWPTRI is
cleared when this register is read.
PRDIV:
The PRDIV bit is read to determine the remote defect indication state. When PRDIV is a
logic one, the S/UNI-8x155 has declared path RDI.
PAISV:
The PAISV bit is read to determine the path AIS state. When PAISV is a logic one, the
S/UNI-8x155 has declared path AIS.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
169
PMC [ PMC-SIERRA, INC ]
