S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
LRDIDET:
The LRDIDET bit determines the line RDI alarm detection algorithm. When LRDIDET is
set to logic one, line RDI is declared when a 110 binary pattern is detected in bits 6, 7 and 8
of the K2 byte for three consecutive frames. When LRDIDET is set to logic zero, line RDI
is declared when a 110 binary pattern is detected in bits 6, 7 and 8 of the K2 byte for five
consecutive frames.
AISDET:
The AISDET bit determines the line AIS alarm detection algorithm. When AISDET is set
to logic one, line AIS is declared when a 111 binary pattern is detected in bits 6, 7 and 8 of
the K2 byte for three consecutive frames. When AISDET is set to logic zero, line AIS is
declared when a 111 binary pattern is detected in bits 6, 7 and 8 of the K2 byte for five
consecutive frames.
ALLONES:
The ALLONES bit controls automatically forcing the SONET/SDH frame passed to
downstream blocks to logical all-ones whenever line AIS is detected. When ALLONES is
set to logic one, the SONET/SDH frame is forced to logic one immediately when the line
AIS alarm is declared. When line AIS is removed, the downstream data stream is
immediately returned to carrying the receive data. When ALLONES is set to logic zero, the
downstream data stream always carry the receive data regardless of the line AIS alarm state.
BIPWORD:
The BIPWORD bit controls the accumulation of B2 errors. When BIPWORD is logic one,
the B2 error event counter is incremented only once per frame whenever one or more B2 bit
errors occur during that frame. When BIPWORD is logic zero, the B2 error event counter
is increment for each and every B2 bit error that occurs during that frame.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
149
PMC [ PMC-SIERRA, INC ]
