S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x018, 0x118, 0x218, 0x318, 0x418, 0x518, 0x618, 0x718:
RLOP Control/Status
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R
Function
BIPWORD
ALLONES
AISDET
LRDIDET
BIPWORDO
FEBEWORD
LAISV
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
X
X
R
LRDIV
LRDIV:
The LRDIV bit is read to determine the remote defect indication state of the RLOP. When
LRDIV is high, the RLOP has declared line RDI.
LAISV:
The LAISV bit is read to determine the line AIS state of the RLOP. When LAISV is high,
the RLOP has declared line AIS.
FEBEWORD:
The FEBEWORD bit controls the accumulation of FEBEs. When FEBEWORD is high, if
the FEBE event has a value from 1 to 4, the FEBE event counter is incremented for each
and every FEBE bit. However, if the FEBE event has a value greater then 4 and is valid,
the FEBE event counter is incremented by 4. When FEBEWORD is low, the FEBE event
counter is incremented for each and every FEBE bit that occurs during that frame (the
counter can be incremented up to 24.).
BIPWORDO:
The BIPWORDO bit controls the indication of B2 errors reported to the TLOP block for
insertion as FEBEs. When BIPWORDO is logic one, the BIP errors are indicated once per
frame whenever one or more B2 bit errors occur during that frame. When BIPWORDO is
logic zero, BIP errors are indicated once for every B2 bit error that occurs during that frame.
The accumulation of B2 error events functions independently and is controlled by the
BIPWORD register bit.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
148
PMC [ PMC-SIERRA, INC ]
