S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x012, 0x112, 0x212, 0x312, 0x412, 0x512, 0x612, 0x712:
RSOP Section BIP-8 LSB
Bit
Type
R
R
R
R
R
R
R
R
Function
SBE[7]
SBE[6]
SBE[5]
SBE[4]
SBE[3]
SBE[2]
SBE[1]
SBE[0]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
Register 0x013, 0x113, 0x213, 0x313, 0x413, 0x513, 0x613, 0x713:
RSOP Section BIP-8 MSB
Bit
Type
R
R
R
R
R
R
R
R
Function
SBE[15]
SBE[14]
SBE[13]
SBE[12]
SBE[11]
SBE[10]
SBE[9]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
SBE[8]
SBE[15:0]:
Bits SBE[15:0] represent the number of section BIP-8 errors (individual or block) that have
been detected since the last time the error count was polled. The error count is polled by
writing to either of the RSOP Section BIP-8 Register addresses. Such a write transfers the
internally accumulated error count to the Section BIP-8 registers within approximately 7 µs
and simultaneously resets the internal counter to begin a new cycle of error accumulation.
This transfer and reset is carried out in a manner that ensures that coincident events are not
lost.
The count can also be polled by writing to the S/UNI-8x155 Master Reset and Identity
register (0x000). Writing to register address 0x000 loads all counter registers in all
channels and APS links.
The count can also be polled by writing to the channel Master Interrupt Status register
(offset 0x07). Writing to register offset 0x07 loads all counter registers in the RSOP, RLOP,
RPOP, SPTB, SSTB, RXCP, TXCP, RXFP, and TXFP blocks of the channel.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
145
PMC [ PMC-SIERRA, INC ]
