STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
events per second, and 16,383 far end block error (FEBE) events per
second.
Sꢀ Detects and validates bit-oriented codes in the C-bit parity far end alarm and
control channel.
Sꢀ Terminates the C-bit parity path maintenance data link with an integral HDLC
receiver having a 128-byte deep FIFO buffer with programmable interrupt
threshold. Supports polled or interrupt-driven operation. Selectable none,
one or two address match detection on first byte of received packet.
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Sꢀ Programmable pseudo-random test-sequence detection–(up to 2 -1 bit
length patterns conforming to ITU-T O.151 standards) and analysis features.
DS3 Transmit Section:
Sꢀ Provides the overhead bit insertion for a DS3 stream.
Sꢀ Provides a bit serial clock and data interface, and allows the M-frame
boundary and/or the overhead bit positions to be located via an external
interface
Sꢀ Provides B3ZS encoding.
Sꢀ Generates an B3Zs encoded 100… repeating pattern to aid in pulse mask
testing.
Sꢀ Inserts far end receive failure (FERF), the DS3 alarm indication signal (AIS)
and the idle signal when enabled by internal register bits.
Sꢀ Provides optional automatic insertion of far end receive failure (FERF) on
detection of loss of signal (LOS), out of frame (OOF), alarm indication signal
(AIS) or red alarm condition.
Sꢀ Provides diagnostic features to allow the generation of line code violation
error events, parity error events, framing bit error events, and when enabled
for the C-bit parity application, C-bit parity error events, and far end block
error (FEBE) events.
Sꢀ Supports insertion of bit-oriented codes in the C-bit parity far end alarm and
control channel.
Sꢀ Optionally inserts the C-bit parity path maintenance data link with an integral
HDLC transmitter. Supports polled and interrupt-driven operation.
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
7
PMC [ PMC-SIERRA, INC ]
