STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
Sꢀ Provides programmable pseudo-random test sequence generation (up to
32
2 -1 bit length sequences conforming to ITU-T O.151 standards) or any
repeating pattern up to 32 bits. The test pattern can be framed or unframed.
Diagnostic abilities include single bit error insertion or error insertion at bit
-1
-7
error rates ranging from 10 to 10 .
M23 Multiplexer Section:
Sꢀ Multiplexes 7 DS2 bit streams into a single M23 format DS3 bit stream.
Sꢀ Performs required bit stuffing/destuffing including generation and
interpretation of C-bits.
Sꢀ Includes required FIFO buffers for rate adaptation in the multiplex path.
Sꢀ Allows insertion and detection of per DS2 payload loopback requests
encoded in the C-bits to be activated under microprocessor control.
Sꢀ Internally generates DS2 clock for use in integrated M13 or C-bit parity
multiplex applications. Alternatively accepts external DS2 clock reference.
Sꢀ Allows per DS2 alarm indication signal (AIS) to be activated or cleared for
either direction under microprocessor control.
Sꢀ Allows DS2 alarm indication signal (AIS) to be activated or cleared in the
demultiplex direction automatically upon loss of DS3 frame alignment or
signal.
Sꢀ Supports C-bit parity DS3 format.
DS2 Framer Section:
Sꢀ Frames to a DS2 (ANSI T1.107 section 8) signal with a maximum average
reframe time of less than 7 ms (as required by TR-TSY-000009 Section 4.1.2
and TR-TSY-000191 Section 5.2).
Sꢀ Detects the DS2 alarm indication signal (AIS) in 9.9 ms in the presence of a
-3
10 bit error rate.
Sꢀ Extracts the DS2 X-bit remote alarm indication (RAI) bit and indicates far end
receive failure (FERF).
Sꢀ Accumulates up to 255 DS2 M-bit or F-bit error events per second.
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
8
PMC [ PMC-SIERRA, INC ]
