STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
the SBIPISO controls the bit rate by accepting data from the EXSBI at the rate of
the individual T1, E1 or DS3 clocks sourced into it.
In addition the SBIPISO generates frame pulses and multiframe pulses for all
T1s, E1s and DS3.
9.30 Scaleable Bandwidth Interconnect SIPO (SBISIPO)
The Scaleable Bandwidth Interconnect Serial to Parallel converter (SBISIPO)
sinks up to 28 T1s, 21 E1s or a DS3 serial clock and data signals and generates
a byte serial stream to the Insert SBI block. The SBISIPO measures the serial
clock against the SBI reference clock and sends this information to the INSBI
block and in turn across the SBI bus to the clock generation slave, SBIPISO. In
this way an accurate representation of the input clock rate is communicated
across the SBI bus.
In addition the SBISIPO generates byte serial streams from frame pulses and
multiframe pulses for all T1s, E1s and DS3.
9.31 JTAG Test Access Port
The JTAG Test Access Port block provides JTAG support for boundary scan.
The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST
instructions are supported. The TEMAP identification code is 553650CD
hexadecimal.
9.32 Microprocessor Interface
The Microprocessor Interface Block provides normal and test mode registers, the
interrupt logic, and the logic required to connect to the Microprocessor Interface.
The normal mode registers are required for normal operation, and test mode
registers are used to enhance the testability of the TEMAP.
The Register Memory Map in Table 10 shows where the normal mode registers
are accessed. The registers are organized so that backward software
compatibility with existing PMC devices is optimized. The resulting register
organization splits into sections: Master configuration registers, 28 sets of T1/E1
Framer registers, DS3 M13 multiplexing registers, SONET/SDH mapping
registers and SBI registers.
On power up reset the TEMAP defaults to 28 T1 framers multiplexed into the
M13 multiplexer using the DS3 M23 multiplex format. For proper operation some
register configuration is necessary. System side access defaults to the SBI bus
without any tributaries enabled which will leave the SBI Drop bus tristated. By
default interrupts will not be enabled, automatic alarm generation is disabled, a
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101
PMC [ PMC-SIERRA, INC ]
