STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
Figure 14
- Clock Master: Clear Channel
CTCLK
Receive CLK[1:28]
ED[1:28]
TJAT
ESIF
Egress
System
Interface
Transmit CLK[1:28]
Transmit Data[1:28]
Digital PLL
ECLK[1:28]
ED[x] Timed
to ECLK[x]
TRANSMITTER
Clock Master: Clear Channel mode has no frame alignment therefore no frame
alignment is indicated to the upstream device. ECLK[x] is a continuous clock at
1.544Mb/s for T1 links or 2.048Mb/s for E1 links.
Figure 15
- Clock Slave: Clear Channel
TRANSMITTER
ED[1:28]
TJAT
ESIF
Egress
System
Interface
Transmit CLK[1:28]
Transmit Data[1:28]
Digital PLL
TJAT
FIFO
ECLK[1:28]
Input Timed
to ECLK[x]
In Clock Slave: Clear Channel mode, the egress interface is clocked by the
externally provided egress clock, ECLK[x]. ECLK[x] must be a 1.544 MHz clock
for T1 links or a 2.048 MHz clock for E1 links. In this mode the T1/E1 framers are
bypassed except for the TJAT which may or may not be bypassed depending on
the setting of the TJATBYP bit in the T1/E1 Egress Line Interface Options
register. Typically the TJAT would be bypassed unless jitter attenuation is
required on ECLK[x].
9.26 Ingress System Interface (ISIF)
The Ingress System Interface (ISIF) block provides a system side Clock Master
serial clock and data access for up to 28 T1 or 21 E1 clear channel receive
streams. Control of the system side interface is global to TEMAP and is selected
through the SYSOPT[2:0] bits in the Global Configuration register at address
0001H. The system interface options are serial clock and data or SBI bus.
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
98
PMC [ PMC-SIERRA, INC ]
