STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
The 44.736Mb/s clock is synthesized from the 51.84MHz or 44.928MHz
reference clock, CLK52M. Using either reference clock frequency, the
44.736Mb/s rate is generated by gapping the reference clock in a fixed way.
Timing adjustments are performed by adding or deleting four clocks over the
500uS period.
When the TEMAP is the SBI egress clock master for a link, clocks are sourced
within the TEMAP. Based on buffer fill levels, the EXSBI sends link rate
adjustment commands to the link source indicating that it should send one
additional or one fewer bytes of data during the next 500uS interval. Failure of
the source to respond to these commands will ultimately result in overflows or
underflows which can be configured to generate per link interrupts.
9.28 Insert Scaleable Bandwidth Interconnect (INSBI)
The Insert Scaleable Bandwidth Interconnect block maps up to 28 1.544Mb/s
links, 21 2.048Mb/s links or a single 44.736Mb/s link into the SBI shared bus.
The 1.544Mb/s links can be unframed when sourced directly from the DS3
multiplexer or SONET/SDH mapper, or they can be T1 channelized when
sourced by the T1 framers. The 2.048Mb/s links can be unframed when sourced
directly from the SONET/SDH mapper, or they can be E1 channelized when
sourced by the E1 framers. The 44.736Mb/s link can also be unframed when
sourced directly from the DS3 interface or from the DS3 mapper. The
44.736Mb/s link can be an unchannelized DS3 when sourced from the DS3
framer.
Links inserted into the SBI bus can be timed from the TEMAP or from the far
end. The INSBI makes link rate adjustments by adding or deleting an extra byte
of data over a 500uS interval based on buffer fill levels. Timing adjustments
made by the INSBI are detected by the receiving SBI interface by explicit signals
in the SBI bus structure.
The INSBI optionally sends link rate information across the SBI bus. This
information is used by the receiving SBI interface to create a recovered link clock
which is based on small clock phase adjustments signaled by the INSBI.
9.29 Scaleable Bandwidth Interconnect PISO (SBIPISO)
The Scaleable Bandwidth Interconnect Parallel to Serial converter (SBIPISO)
generates up to 28 T1s, 21 E1s or a DS3 serial clock and data signals from the
byte serial stream provided by the Extract SBI block. The generated clock rate
can be controlled with commands from the EXSBI. In clock slave mode the
generated clock will be increased or decreased in small increments based on
FIFO fill levels within the EXSBI or directly with clock rate commands from the far
end device who is mastering the clock across the SBI bus. In clock master mode
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
100
PMC [ PMC-SIERRA, INC ]
