STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
The ingress Clock Master: Clear Channel interface mode is selected via the
IMODE[1:0] bits in the T1/E1 Ingress Serial Interface Mode Select register.
Figure 16
- Clock Master: Clear Channel
RECEIVER
ID[x]Timed to
ICLK[x]
ISIF
Ingress
System
Interfac e
ID[1:28]
RJAT
Receive Data[1:28]
Receive CLK[1:28]
Digita l Jitter
ICLK[ 1:28]
Attenuator
In Clock Master: Clear Channel mode, the ingress clock (ICLK[x]) is a jitter
attenuated version of the 1.544 MHz or 2.048 MHz receive clock coming from
either the M13 multiplex or SONET/SDH demapper. The ingress data appears
on ID[x].
9.27 Extract Scaleable Bandwidth Interconnect (EXSBI)
The Extract Scaleable Bandwidth Interconnect block demaps up to 28 1.544Mb/s
links, 21 2.048Mb/s links or a single 44.736Mb/s link from the SBI shared bus.
The 1.544Mb/s links can be unframed when used in a straight multiplexer or
mapper application, or they can be T1 framed and channelized for insertion into
the DS3 multiplex or SONET/SDH mapping. The 2.048Mb/s links can be
unframed when used in a straight mapper application, or they can be E1 framed
and channelized for insertion into the SONET/SDH mapping. The 44.736Mb/s
link can also be unframed for mapping into SONET/SDH or it can be DS3
unchannelized when the TEMAP is used as a DS3 framer.
All egress links extracted from the SBI bus can be timed from the source or from
the TEMAP. When Timing is from the source the EXSBI commands the PISO to
generate 1.544Mb/s, 2.048Mb/s or 44.736Mb/s clocks slaved to the arrival rate
of the data or from timing link rate adjustments provided from the source and
carried with the links over the SBI bus. The 1.544Mb/s clock is synthesized from
the 19.44MHz reference clock, SREFCLK, by dividing the clock by either 12 or
13 in a fixed sequence that produces the nominal 1.544Mb/s rate. The
2.048Mb/s clock is synthesized from the 19.44MHz reference clock by dividing
the clock by either 9 or 10 in a fixed sequence that produces the nominal
2.048Mb/s rate. Timing adjustments are made over 500uS intervals and are
done by either advancing or retarding the phase or by adding or deleting a whole
1.544Mb/s or 2.048Mb/s clock cycle over the 500uS period.
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
99
PMC [ PMC-SIERRA, INC ]
