STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
Table 9
- DS3 synchronizer bit stuffing algorithm.
Row Number
Normal or DS3 AIS
Run Faster
Run Slower
1
2
3
4
5
6
7
8
9
S
S
I
S
S
I
S
S
I
S
S
I
S
I
I
S
I
S
S
I
S
S
S
S
S
S
I
Under microprocessor control, the incoming DS3 stream can be overwritten with
the framed DS3 AIS. When asserting DS3 AIS, a nominal stuff pattern is used
as illustrated above. Please refer to the D3MD functional description section for
a description of the DS3 AIS frame.
The D3MA outputs the STS-1 (STM-0/AU3) with the mapped DS3 onto the Line
Add bus, LADATA[7:0].
9.25 Egress System Interface (ESIF)
The Egress System Interface (ESIF) block provides system side serial clock and
data access for up to 28 T1 or 21 E1 transmit streams. Control of the system
side interface is global to TEMAP and is selected through the SYSOPT[2:0] bits
in the Global Configuration register at address 0001H. The system interface
options are serial clock and data or SBI bus.
There are two serial clock and data egress interface modes provided by TEMAP,
Clock Master: Clear Channel and Clock Slave: Clear Channel. The egress serial
clock and data interface clocking modes are selected via the EMODE[2:0] bits in
the T1/E1 Egress Serial Interface Mode Select register.
In all egress Clock Master modes the transmit clock can be sourced from either
the common transmit clock, CTCLK, one of the two recovered clocks,
RECVCLK1 and RECVCLK2, or the received clock for that link. The selection
between CTCLK, RECVCLK1 and RECVCLK2 as the reference transmit clock is
the same for all T1/E1 framers. Jitter attenuation can be applied to the master
mode clock with the TJAT.
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
97
PMC [ PMC-SIERRA, INC ]
