PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
multiframe. The IC1J1[1] (IC1J1[2], IC1J1[3], IC1J1[4]) signal pulses high to mark
the single J1 byte of the VC4. This diagram applies to input buses in AU4 mode,
regardless of whether individual tributary payload processors are configured for
TUG3 or TU3 mode. The four input buses can be independently configured to
handle STS-1/AU3 or AU4 and the SPE/VC alignments of the input buses may
be different. However, the transport frame alignments of the four input buses
must be identical. That is, the C1 portion of all the IC1J1[4:1] signals must be
coincident.
Figure 21
- STM-1 Input Bus Timing - AU4 Case
SCLK
IC1J1[n]
IPL[n]
••••
ITMF[n]
(ITMFH4=1)
ID[7:0] (n=1)
ID[15:8] (n=2)
ID[23:16] (n=3)
ID[31:24] (n=4)
A1 A1 A1 A2 A2 A2 C1
X
X
H4
H1 H1 H1 H2 H2 H2
Negative stuff for VC4 which
happens to carry the J1 byte
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
393
PMC [ PMC-SIERRA, INC ]
