PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
directly follow the C1 bytes. Other alignments are possible. The four input buses
can be independently configured to handle STS-1/AU3 or AU4 and the SPE/VC
alignments of the input buses may be different. However, the transport frame
alignments of the four input buses must be identical. That is, the C1 portion of all
the IC1J1[4:1] signals must be coincident. This diagram also applies to the AU3
mode as it is equivalent to STS-1 mode, except for nomenclature.
Figure 20
- STM-1 Input Bus Timing - STS-1 / AU3 (VT/TU Pointer
Interpretation Disabled)
SCLK
IC1J1[n]
IPL[n]
ITMF[n]
(ITMFH4=0)
••••
ITV5[n]
ITPL[n]
A2 C1 C1 C1 J1 J1 J1 V1 V1 V1 V1 V1 V1 V1
H1 H1 H1 H2 H2 H2 H3 H3 H3
No stuff event
J2 V5
ID[7:0] (n=1)
ID[15:8] (n=2)
ID[23:16] (n=3)
ID[31:24] (n=4)
Implicit location
of STS-1 SPE
J1 bytes
J2 byte VT #1, STS-1 #1
V5 byte VT #1, STS-1 #2
V1 bytes VT #2
V1 byte VT #1, STS-1 #1
V1 byte VT #1, STS-1 #2
V1 byte VT #1, STS-1 #3
Figure 21 shows timing relationships of the various input signals in the AU4 mode
associated with each of the four input buses when the TUPP+622 is in STM-1
(STS-3) input interface mode (IHSMODEB set high) (n is {1, 2, 3, 4}). Data on
ID[7:0] (ID[15:8], ID[23:16], ID[31:24]) is sampled on the rising edge of SCLK.
The bytes forming the AU4 virtual container are identified by the IPL[1] (IPL[2],
IPL[3], IPL[4]) signal being set high. This example shows a negative stuff
occurring for the VC4. The IC1J1[1] (IC1J1[2], IC1J1[3], IC1J1[4]) signal pulses
high while IPL[1] (IPL[2], IPL[3], IPL[4]) is set low to mark the position of the
single C1 byte in the STM-1 transport envelope. The ITMF[1] (ITMF[2], ITMF[3],
ITMF[4]) signal is selectable to mark the third byte after J1, or the H4 byte in the
last (fourth) frame of a tributary multiframe. In this diagram, ITMF[1] (ITMF[2],
ITMF[3], ITMF[4]) is shown to be marking the final H4 byte of the tributary
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392
PMC [ PMC-SIERRA, INC ]
